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r10ds0107ej0100 rev.1.00 page 1 of 17 feb. 23, 2012 preliminary datasheet r1ex24016asas0i r1ex24016atas0i two-wire serial interface 16k eeprom (2-kword ? 8-bit) description r1ex24xxx series are two-wire serial interface eeprom (e lectrically erasable and pr ogrammable rom). they realize high speed, low power consumption and a high level of reliability by employing advanced monos memory technology and cmos process and low voltage circuitry technology. they also have a 16-byte page programming function to make their write operation faster. features ? single supply: 1.8 v to 5.5 v ? two-wire serial interface (i 2 c serial bus) ? clock frequency: 400 khz ? power dissipation: ? standby: 2 ? a (max) ? active (read): 1 ma (max) ? active (write): 3.0 ma (max) ? automatic page write: 16-byte/page ? write cycle time: 5 ms ? endurance: 1,000k cycles @25 ? c ? data retention: 100 years @25 ? c ? small size packages: so p-8pin , tssop 8-pin ? shipping tape and reel ? tssop 8-pin: 3,000 ic/reel ? sop 8-pin: 2,500 ic/reel ? temperature range: ? 40 to +85 ?c ? lead free products. r10ds0107ej0100 rev.1.00 feb. 23, 2012
r1ex24016asas0i/r1ex24016atas0i r10ds0107ej0100 rev.1.00 page 2 of 17 feb. 23, 2012 ordering information orderable part numbers internal organization package shipping tape and reel r1ex24016asas0i#s0 16k bit (2048 ? 8-bit) 150 mil 8-pin plastic sop prsp0008df-b (fp-8dbv) lead free 2,500 ic/reel r1ex24016atas0i#s0 16k bit (2048 ? 8-bit) 8-pin plastic tssop ptsp0008jc-b (ttp-8dav) lead free 3,000 ic/reel pin arrangement /8-pin tssop 1 2 3 4 8 7 6 5 a0 a1 a2 v ss v cc wp scl sda (top view) 8-pin sop pin description pin name function a0 to a2 device address scl serial clock input sda serial data input/output wp write protect v cc power supply v ss ground block diagram control logic high voltage generator address generator x decoder y decoder memory array y-select & sense amp. serial-parallel converter v cc v ss wp a0, a1, a2 scl sda
r1ex24016asas0i/r1ex24016atas0i r10ds0107ej0100 rev.1.00 page 3 of 17 feb. 23, 2012 absolute maximum ratings parameter symbol value unit supply voltage relative to v ss v cc ? 0.6 to +7.0 v input voltage relative to v ss vin ? 0.5 * 2 to +7.0 * 3 v operating temperature range * 1 topr ? 40 to +85 ?c storage temperature range tstg ? 55 to +125 ?c notes: 1. including electrical c haracteristics and data retention. 2. vin (min): ? 3.0 v for pulse width ? 50 ns. 3. should not exceed v cc + 1.0 v. dc operating conditions parameter symbol min typ max unit v cc 1.8 ?? 5.5 v supply voltage v ss 0 0 0 v input high voltage v ih v cc ? 0.7 ? v cc + 0.5 v input low voltage v il ? 0.3 * 1 ? v cc ? 0.3 v operating temperature topr ? 40 ? +85 ?c notes: 1. v il (min): ? 1.0 v for pulse width ? 50 ns. dc characteristics (ta = ? 40 to +85 ? c, v cc = 1.8 v to 5.5 v) parameter symbol min typ max unit test conditions input leakage current i li ? ? 2.0 ? a v cc = 5.5 v, vin = 0 to 5.5 v output leakage current i lo ? ? 2.0 ? a v cc = 5.5 v, vout = 0 to 5.5 v standby v cc current i sb ? 1.0 2.0 ? a vin = v ss or v cc read v cc current i cc1 ? ? 1.0 ma v cc = 5.5 v, read at 400 khz write v cc current i cc2 ? ? 3.0 ma v cc = 5.5 v, write at 400 khz v ol2 ? ? 0.4 v v cc = 2.7 to 5.5 v, i ol = 3.0 ma output low voltage v ol1 ? ? 0.2 v v cc = 1.8 to 2.7 v, i ol = 1.5 ma capacitance (ta = +25 ? c, f = 1 mhz) parameter symbol min typ max unit test conditions input capacitance (a0 to a2, scl, wp) cin * 1 ? ? 6.0 pf vin = 0 v output capacitance (sda) c i/o * 1 ? ? 6.0 pf vout = 0 v note: 1. not 100 ? tested. memory cell characteristics (v cc = 1.8 v to 5.5 v) ta=25 ?c ta=85 ?c notes endurance 1,000k cycles min. 100k cycles min 1 data retention 100 years min. 10 years min. 1 note: 1. not 100 ? tested.
r1ex24016asas0i/r1ex24016atas0i r10ds0107ej0100 rev.1.00 page 4 of 17 feb. 23, 2012 ac characteristics (ta = ? 40 to +85 ? c, v cc = 1.8 to 5.5 v) test conditions ? input pules levels: ? v il = 0.2 ? v cc ? v ih = 0.8 ? v cc ? input rise and fall time: ? 20 ns ? input and output timing reference levels: 0.5 ? v cc ? output load: ttl gate + 100 pf parameter symbol min typ max unit notes clock frequency f scl ? ? 400 khz clock pulse width low t low 1200 ? ? ns clock pulse width high t high 600 ? ? ns noise suppression time t i ? ? 50 ns 1 access time t aa 100 ? 900 ns bus free time for next mode t buf 1200 ? ? ns start hold time t hd.sta 600 ? ? ns start setup time t su.sta 600 ? ? ns data in hold time t hd.dat 0 ? ? ns data in setup time t su.dat 100 ? ? ns input rise time t r ? ? 300 ns 1 input fall time t f ? ? 300 ns 1 stop setup time t su.sto 600 ? ? ns data out hold time t dh 50 ? ? ns write protect hold time t hd.wp 1200 ? ? ns write protect setup time t su.wp 0 ? ? ns write cycle time t wc ? ? 5 ms 2 notes: 1. not 100 ? tested. 2. t wc is the time from a stop condition to the end of internally controlled write cycle.
r1ex24016asas0i/r1ex24016atas0i r10ds0107ej0100 rev.1.00 page 5 of 17 feb. 23, 2012 timing waveforms bus timing t f 1/f scl t high t su.sta t hd.sta t hd.dat t su.dat t su.sto t buf t dh t aa t low t r scl wp sda (in) sda (out) t su.wp t hd.wp write cycle timing scl sda d0 in write data ack (address (n)) t wc (internally controlled) stop condition start condition
r1ex24016asas0i/r1ex24016atas0i r10ds0107ej0100 rev.1.00 page 6 of 17 feb. 23, 2012 pin function serial clock (scl) the scl pin is used to control serial input/output data timing. the scl input is used to positive edge clock data into eeprom device and negative edge clock data out of each device. maximum clock rate is 400 khz. serial input/output data (sda) the sd a pin is bidirectional for serial data transfer. the sda pin needs to be pulled up by resistor as that pin is open- drain driven structure. use proper resistor value for your system by considering v ol , i ol and the sda pin capacitance. except for a start condition and a stop condition which will be discussed later, the sda transition needs to be completed during the scl low period. data validity (sda data chang e timing waveform) scl sda data change data change note: high-to-low and low-to-high change of sda should be done during the scl low period.
r1ex24016asas0i/r1ex24016atas0i r10ds0107ej0100 rev.1.00 page 7 of 17 feb. 23, 2012 device address (a0, a1, a2) one device can be wired for one common data bus line as maximum. all device address are used for memory address, corresponding device address pins must not be fixed. pin connections for a0 to a2 pin connection memory size max connect number a2 a1 a0 note 16k bit 1 ? * 1 ? * 1 ? * 1 use a0,a1,a2 for memory address a8,a9 and a10 note: 1. floating state can be possible. write protect (wp) when the write protect pin (wp) is high, the write protection feature is enabled and operates as shown in the following table. also, acknowledgment "0" is outputted after inputting device address and memory address. after inputting write data, acknowledgment "1"" (no ack) is outputted. when the wp is low, write operation for all memory arrays are allowed. the read op eration is always activated irrespective of the wp pin status. the wp pin is internally pulled-down to vss. write ope rations for all memory array are allowed if unconnected. write protect area write protect area wp pin status 16k bit v ih full (16k bit) v il normal read/write operation
r1ex24016asas0i/r1ex24016atas0i r10ds0107ej0100 rev.1.00 page 8 of 17 feb. 23, 2012 functional description start condition a high-to-low transition of the sda with the scl high is needed in order to start read, write operation (see start condition and stop condition). stop condition a low-to -h igh transition of the sda with the scl high is a stop condition. the stand-by operation starts after a read sequence by a stop condition. in the case of write operation, a stop condition te rminates the write data inputs and place the device in a internally-timed write cycle to the memories. after the internally-timed write cycle which is specified as t wc , the device enters a standby mode (see write cycle timing). start condition and stop condition scl sda (in) stop condition start condition acknowledge all addresses and data words are serially transmitted to and from in 8-bit words. the receiver sends a zero to acknowledge that it has received each word. this happens during ninth clock cycl e. the transmitter keeps bus open to receive acknowledgment from the receiver at the ninth cloc k. in the write operation, eeprom sends a zero to acknowledge after receiving every 8-bit words. in th e read operation, eeprom se nds a zero to acknowledge after receiving the device address word. afte r sending read data, the eeprom waits acknowledgment by k eeping bus open. if the eeprom receives zero as an acknowledge, it sends r ead data of next address. if the eeprom receives acknowledgment "1" (no acknowledgment) and a following stop condition, it stops the read operation and enters a stand-by mode. if the eeprom receives neither acknow ledgment "0" nor a stop condi tion, the eeprom keeps bus open without sending read data. acknowledge timing waveform scl sda in sda out 12 8 9 acknowledge out
r1ex24016asas0i/r1ex24016atas0i r10ds0107ej0100 rev.1.00 page 9 of 17 feb. 23, 2012 device addressing the eeprom device requires an 8-bit device address word follo wing a start condition to enable the chip for a read or a write operation. the device address word consists of 4-bit device code, 3-bit device address code and 1-bit read/write(r/w) code. the most significant 4-bit of the de vice address word are used to distinguish device type and this eeprom uses ?1010? fixed code. the device address code is followed by the 3-bit memory address in the order of a10, a9, a8. the eighth bit of the device address word is the read/write(r/w) bit. a write operation is initiated if this bit is low and a read operation is initiated if this bit is high. the eeprom turns to a stand-by state if the device code is not ?1010?. device address word device address word (8-bit) device code (fixed) device address code r/w code * 1 16k 1 0 1 0 a10 a9 a8 r/w note: 1. r/w=?1? is read and r/w = ?0? is write.
r1ex24016asas0i/r1ex24016atas0i r10ds0107ej0100 rev.1.00 page 10 of 17 feb. 23, 2012 write operations (wp=low) byte write: (write operation during wp=low status) a write operation requires an 8-bit device address word with r/w = ?0?. then the eeprom sends acknowledgment "0" at the ninth clock cycle. after th ese, the 16kbit eeprom receives 8-bit memo ry address words. upon receipt of this memory address, the eeprom outputs acknowledgment "0" and receives a following 8-bit write data. after receipt of write data, the eeprom ou tputs acknowledgment "0". if the ee prom receives a stop condition, the eeprom enters an internally-timed write cycle and terminates receipt of sc l, sda inputs until completion of the write cycle. the eeprom returns to a standby mode after completion of the write cycle. byte write operation device address memory address (n) write data (n) 16k 1010 w a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 stop start ack ack r/w ack wp page write: (write operation during wp=low status) the eeprom is capable of the page write operation which allo ws any number of bytes up to 16 bytes to be written in a single write cycle. the page write is the same sequence as the byte write except for inputting the more write data. the page write is initiated by a start condition, device address word, memory address(n) and write data (dn) with every ninth bit acknowledgment. the eeprom enters the page write operation if the eeprom receives more write data (dn+1) instead of receiving a stop cond ition. the a0 to a3 address bits are automatically incremen ted upon receiving write data (dn+1). the eeprom can continue to receive write data up to 16 bytes. if the a0 to a3 address bits reaches the last address of the page, the a0 to a3 address bits will roll over to the first address of the same page and previous write data will be overwritten. upon receiving a stop c ondition, the eeprom stops receiving write data and enters internally-timed write cycle. page write operation device address memory address (n) write data (n+m) write data (n) 16k 1010 w a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d5 d4 d3 d2 d1 d0 stop start ack ack ack ack r/w wp
r1ex24016asas0i/r1ex24016atas0i r10ds0107ej0100 rev.1.00 page 11 of 17 feb. 23, 2012 write operations (wp=high) byte write: (write operation during wp=high status) a write operation requires an 8-bit device address word with r/w = ?0?. then the eeprom sends acknowledgment "0" at the ninth clock cycle. after these, the 1 6kbit eeprom receives 8-bit me mory address words. upon receipt of this memory address, the eeprom outputs acknowledgment "0 ". after receipt of 8-bit write data, the eeprom outputs acknowledgment "1" (no ack) . then the eeprom write operations are not allowed. byte write operation device address memory address (n) write data (n) 16k 1010 w a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 stop start ack ack r/w no ack wp page write: (write operation during wp=high status) the page write is the same sequence as the byte write. the page write is initiated by a start condition, device address word and memory address(n) with every ninth bit acknowledgment"0". but after inputting write data(dn) , the eeprom outputs acknowledgment "1" (no ack ). then the eeprom write operations are not allowed. page write operation device address memory address (n) write data (n+m) write data (n) 16k 1010 w a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d5 d4 d3 d2 d1 d0 stop start ack no ack ack r/w wp no ack
r1ex24016asas0i/r1ex24016atas0i r10ds0107ej0100 rev.1.00 page 12 of 17 feb. 23, 2012 acknowledge polling: acknowledge polling feature is used to show if the eeprom is in a internally-timed write cycle or not. this feature is initiated by the stop condition after inputting write data. this requires the 8-bit device address word following the start condition during a internally-timed write cycle. acknowledge polling will operate when the r/w code = ?0?. acknowledgment ?1? (no acknowledgment) shows the eep rom is in a internally-timed write cycle and acknowledgment ?0? shows that the internally-timed write cycle has completed. see write cycle polling using ack. write cycle polling using ack send write command send stop condition to initiate write cycle send start condition send device address word with r/w = 0 send memory address send start condition send stop condition send stop condition proceed random address read operation proceed write operation next operation is addressing the memory ye s ye s no no ack returned
r1ex24016asas0i/r1ex24016atas0i r10ds0107ej0100 rev.1.00 page 13 of 17 feb. 23, 2012 read operation there are three read operations: current address read, ran dom read, and sequential read. read operations are initiated the same way as write operations with the exception of r/w = ?1?. current address read: the internal address counter maintains the last address accessed during the la st read or write operation, with incremented by one. current address read accesses the address kept by the internal address counter. after receiving a start condition and the device address word (r/w is ?1?), the eeprom outputs the 8-bit current address data from the most significant bit following acknowledgment ?0?. if the eeprom receives acknowledgment ?1? (no acknowledgment) and a following stop condition, the eeprom stops the read operation and is turned to a standby state. in case the eeprom has accessed the last address of the last page at previous read operation, the current address will roll over and returns to zero address. in case the eeprom ha s accessed the last address of the page at previous write operation, the current address will roll over within page addres sing and returns to the first address in the same page. the current address is valid while power is on. the current address after power on will be indefinite. the random read operation described below is necessary to define the memory address. current address read operation 16k device address read data (n+1) start stop 1010 r d7 d6 d5 d4 d3 d2 d1 d0 ack no ack r/w 1* 1* 1* notes:1*don't care bit
r1ex24016asas0i/r1ex24016atas0i r10ds0107ej0100 rev.1.00 page 14 of 17 feb. 23, 2012 random read: this is a read operation with defined re ad address. a random read requires a dummy write to set read address. the eeprom receives a start condition, de vice address word (r/w=0) and memory address 8-bit sequentially. the eeprom outputs acknowledgment ?0? after receiving memory address then enters a current address read with receiving a start condition. the eeprom outputs the read data of the ad dress which was defined in the dummy write operation. after receiving acknowledg ment ?1?(no acknowledgment) and a following stop condition, the eeprom stops the random read operation and returns to a standby state. random read operation notes: 1. don't care bit device address device address memory address (n) read data (n) 16k 10 10 1010 r w a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 stop start start ack no ack ack r/w ack r/w dummy write current address read * 1 * 1 * 1 sequential read: sequential reads are initiated by either a current addre ss read or a random read. if the eeprom receives acknowledgment ?0? after 8-bit r ead data, the read address is incremented and the next 8-bit read data are coming out. this operation can be continued as long as the eeprom receives acknowledgment ?0?. the address will roll over and returns address zero if it reaches the last address of the last page. the sequential read can be continued after roll over. the sequential read is terminated if the eeprom receives acknowledgment ?1 ? (no acknowledgment) and a following stop condition. sequential read operation device address read data (n+m) read data (n) read data (n+1) read data (n+2) 16k 1010 r d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 stop start ack ack no ack ack r/w ack *1: don't care bit *1 *1 *1
r1ex24016asas0i/r1ex24016atas0i r10ds0107ej0100 rev.1.00 page 15 of 17 feb. 23, 2012 notes data protection at v cc on/off when v cc is turned on or off, noise on the scl and sda inputs generated by external circuits (cpu, etc) may act as a trigger and turn the eeprom to unintentional program mode . to prevent this unintentional programming, this eeprom has a power on reset function. be careful of the notices described below in order for the power on reset function to operate correctly. ? scl and sda should be fixed to v cc or v ss during v cc on/off. low to high or high to low transition during v cc on/off may cause the trigger for the unintentional programming. ? v cc should be turned off after the eeprom is placed in a standby state. ? v cc should be turned on from the ground level(v ss ) in order for the eeprom not to enter the unintentional programming mode. ? v cc turn on rate should be slower than 2 ? s/v. noise suppression time this eeprom have a noise suppression function at scl and sd a inputs, that cut noise of width less than 50 ns. be careful not to allow noise of width more than 50 ns.
r1ex24016asas0i/r1ex24016atas0i r10ds0107ej0100 rev.1.00 page 16 of 17 feb. 23, 2012 package dimensions r1ex24016asas0i (prsp0008df-b / previous code: fp-8dbv) a l e c 1 b 1 d e a 2 b p c x y h e z l 1 4.89 1.06 0.25 0 8 6.02 0.15 0.20 0.25 0.45 0.102 0.14 0.254 3.90 0.406 0.60 0.889 1.73 reference symbol dimension in millimeters min nom max 5.15 a 1 0.35 0.40 6.20 5.84 1.27 0.10 0.69 index mark e 1 y xm p *3 *2 *1 f 4 85 d e h a z b p terminal cross section ( ni/pd/au plating ) b c detail f 1 1 l l a note) 1. dimensions" *1 (nom)"and" *2" do not include mold flash. 2. dimension" *3"does not include trim offset. e p-sop8-3.9x4.89-1.27 0.08g mass[typ.] fp-8dbv prsp0008df-b renesas code jeita package code previous code
r1ex24016asas0i/r1ex24016atas0i r10ds0107ej0100 rev.1.00 page 17 of 17 feb. 23, 2012 r1ex24016atas0i (ptsp0008jc-b / previous code: ttp-8dav) a l e c 1 b 1 d e a 2 b p c x y h e z l 1 3.00 1.00 0.13 0 8 6.40 0.10 0.15 0.20 0.25 0.03 0.07 0.10 4.40 0.40 0.50 0.60 1.10 reference symbol dimension in millimeters min nom max 3.30 a 1 0.15 0.20 6.60 6.20 0.65 0.10 0.805 *1 85 e *2 index mark 14 *3 p mx y f a d e h z b detail f 1 1 a l l p terminal cross section ( ni/pd/au plating ) c b note) 1. dimensions" *1 (nom)"and" *2" do not include mold flash. 2. dimension" *3"does not include trim offset. e p-tssop8-4.4x3-0.65 0.034g mass[typ.] ttp-8dav ptsp0008jc-b renesas code jeita package code previous code
all trademarks and registered trademarks are t he property of their respective owners. c - 1 revision history r1ex24016asas0i/r 1ex24016atas0i data sheet description rev. date page summary 0.01 dec. 28, 2007 ? initial issue 0.02 jan. 08, 2009 p1 p4 p5 features endurance cycles change 10 6 cycles to 1,000k cycles @25c. data retentions years change 10 years to 100years@25c. memory cell characteristics new is described. ac characteristics erase/write endurance is deleted. notes1. change not 100% tested. notes3. deleted. 1.00 feb. 23, 2012 ? p7 p9 p14 p15 delete preliminary addition of write protect description the wp pin is internally pulled-down to vss. write operations for all memory array are allowed if unconnected. delete the sentence or device address code doesn?t coincide with status of the correspond hard- wired device address pins a0 to a2. change the sentence device address word (r/w=0) and memory address 2 ? 8-bit sequentially. to device address word (r/w=0) and memory address 8-bit sequentially. change note v cc turn on speed should be longer than 10 ? s. to v cc turn on rate should be slower than 2 ? s/v.
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(note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-o wned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 1 harbourfront avenue, #06-10, keppel bay tower, singapore 098632 tel: +65-6213-0200, fax: +65-6278-8001 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 11f., samik lavied' or bldg., 720-2 yeoksam-dong, kangnam-ku, seoul 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2012 renesas electronics corporation. all rights reserved. colophon 1.1

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